Digital Logic Fundamentals
Senior 4 · ICT
Digital Logic Fundamentals
Lesson 3 of 5
25 min
In lesson 1 you added binary numbers column by column: in each column, 1 + 1 gives a sum bit of 0 and a carry of 1. A processor does exactly this, billions of times a second, with a small circuit of gates for each column. In this lesson you learn to read and draw such circuits, and you design the first piece of a computer's adder yourself.
Definition
Logic circuit: gates joined by wires so that the outputs of some gates are the inputs of others. In a combinational circuit the outputs depend only on the present inputs (no memory).
Intermediate output: the output of a gate inside the circuit, labelled with a letter (P, Q) so that the circuit can be analysed step by step.
Junction: a dot where wires are joined. Wires that cross without a dot are not connected.
Read the expression the way it is evaluated: brackets, then NOT, then AND, then OR. Each operation is one gate, and the operation done last is the gate that gives the output.
For , the last operation is the OR, so an OR gate gives . Its two inputs are (an AND gate) and (a NOT gate): three gates in all.
To analyse a circuit, work from the inputs to the output. Label every intermediate output, write its expression, then substitute.
Worked example 1: the truth table of the circuit above
Three inputs give rows. List them in binary counting order (000 to 111) so none is missed, then fill the intermediate columns before .
| A | B | C | |||
|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 |
in four rows: whenever or is 1, except when and are both 1.
Press Run to let Python work through all 8 rows and compare its output with worked example 1. Each line inside the loops is one gate. You will write programs like this yourself in Unit 4.
Design follows five steps: (1) name the inputs and outputs; (2) write the truth table; (3) find an expression for each output; (4) draw the circuit; (5) test every row.
To add two bits and , the circuit needs two outputs: the sum bit and the carry bit .
| A | B | A + B in binary | Carry C | Sum S |
|---|---|---|---|---|
| 0 | 0 | 00 | 0 | 0 |
| 0 | 1 | 01 | 0 | 1 |
| 1 | 0 | 01 | 0 | 1 |
| 1 | 1 | 10 | 1 | 0 |
The column (0, 1, 1, 0) is XOR and the column (0, 0, 0, 1) is AND, so and . Both gates share the same two inputs.
A half adder cannot accept a carry from the column to its right. A full adder has a third input, the carry-in , and computes and ; it can be built from two half adders and an OR gate. Chaining 8 full adders adds two bytes.
VAM! Physics & Engineering: Convert Boolean Algebra to Gated Circuit, Vice Versa and Truth Tables. Watch how an expression is turned into gates and how a drawn circuit is read back into an expression, then compare with the two methods above.
Worked example 2: draw from an expression, and count the gates
Draw a circuit for .
Gates: OR, NAND, AND, which is 3 gates (or 4 if the NAND is drawn as AND + NOT). Check one row: : , , , .
Warning
A crossing is not a joint. Two wires that cross are connected only if a dot marks the junction. Leaving out a needed dot, or adding a dot where wires only cross, changes the circuit.
Check the operation done last. In the output gate is OR, not AND, because AND is done first.
Tip
Label as you go. Write the expression of every wire on the diagram beside it. Then the expression of the output can be read straight off the last gate, and a truth table needs one column per label.
Open the free online simulator CircuitVerse (no installation needed). Place two Input elements, an XOR gate, an AND gate and two Output elements, and wire up the half adder. Click the inputs to set every combination of 0 and 1 and check the outputs against the truth table. Then build the circuit of worked example 1 and test its eight rows.
Practice
Key points
Sources and credits
This lesson adapts CC BY-SA material and is shared under CC BY-SA 4.0.
# Truth table of Y = NOT(A AND B) AND (B OR C)
print("A B C | P Q | Y")
for A in (0, 1):
for B in (0, 1):
for C in (0, 1):
P = int(not (A and B)) # NAND gate
Q = int(B or C) # OR gate
Y = P and Q # AND gate
print(A, B, C, "|", P, Q, "|", Y)Quick check
In a circuit for Y = A + B·C, which gate gives the output Y?